Which way is better writing a register path in Verilog -

solution 1

reg q; @(posedge clk or negedge rst_n) if (!rst_n)   q <= 1'b0; else   if (en_a)     q <= da;   else if (en_b)     q <= db;   else if (en_c)     q <= dc; 

solution2

reg qw, qr; @(*) if (en_a)   qw = da; else if (en_b)   qw = db; else if (en_c)   qw = dc;  @(posedge clk or negedge rst_n) if (!rst_n)   qr <= 1'b0; else   qr <= qw; 

i use solution 1 lot , can find lot in many other engineers' code. solution 2 seperates combinational logic part , sequencial logic part, classic fsm style.

my question is, (for solution 2)is there actual advantage on solution 1? , difference between 2 solutions?

it partly depends on size of design , synthesizer. large fsm designs 2 block approach uses less area, has better timing, , fewer lines of code equivalent 1 block. this paper cliff cummings goes detail on differences between one, two, 3 block approaches. been recommending style while in older papers here , here. several years go team compared styles our own code , tools; can came same conclusion cliff. should try comparing on own.

the 2 block advantages are:

• see next value of flop before clock in waveform or display statement. 1 block need calculate values.
• will not accidentally create unintended flip-flop
  • note: there risk of inferring unintended latch, since there few intended latches in design easy spot in reports of linting , synthesis tools. unintended flip-flop harder spot.
• all combinational logic grouped together.
• easier manual eco. fewer lines of code change.
• no need worry accidentally mixing blocking , non-blocking
• for large designs:
  • few lines of code
  • smaller area
  • better timing

the 1 block advantages are:

• generally 1 block slightly more simulation-efficient 2 block - (cliff snug1998sj fsm, page 10)
• will not accidentally infer unintended latch
• when strictly following ieee1364-1995:
  • @(*) added in ieee1364-2001. in ieee1364-1995, every signal external driving signal used in combinational block needed listed in sensitively list.
    • example: @(en_a or en_b or en_c or da or db or dc or qr)
• for small designs:
  • only 1 block at