verilog - Delay between two instantiations of same module -

i want run following code:

module (input a1 ,clock, reset, output aout);  ---- ---- ----  key k1(a1,clock,reset,k1out); // takes around 40 cycles complete   key k2(k1out,clock,reset,k2out);  endmodule 

k1out displayed correctly, k2out not. in fact getting k2out xxxxx. there way provide delay between these 2 instantiations executed in order , can output correctly?

your describing hardware, 2 instances exist in parallel.

you either control clock each block execute sequentially, or build state machine sequence them.

with clock gating (internal key):

module (input a1 ,clock, reset, output aout);  ---- ---- ----  logic [6:0] state; @(posedge clock or posedge reset) begin   if (reset) begin     state <= 'b0;   end   else begin     if (state >= 7'd80) begin       state <= 'b0 ;     end else        state <= state + 1'b1;   end end  wire k1_enable = (state <  7'd40 ); wire k2_enable = (state >= 7'd40);   key k1(a1,   clock,reset,k1out, k1_enable);  key k2(k1out,clock,reset,k2out, k2_enable);  endmodule 

sequential elements of key use:

always @(posedge clock or posedge reset) begin   if (reset) begin     data <= 1'b0;   end   else begin     if (enable) begin       data <= ; //next value     end     //else hold data   end end