system verilog - How do you initialize uvm_mem? -


suppose have input file (someinputdata.txt) loaded in uvm memory declared follows , instantiated somewhere on register block (a class extends uvm_reg_block).

class mymemory extends uvm_mem;    `uvm_object_utils(mymemory)     function new(string name = "mymemory");       super.new(name, 32'h800, 32, "rw", uvm_no_coverage);    endfunction  endclass

i'm not sure if there built-in function load input file uvm_mem.

how efficiently load someinputdata.txt memory?

the uvm_mem class not have mirror of actual memory. have load via front-door or back-door method need define. back-door preferred, need define user-defined backdoor access extending uvm_reg_backdoor class , implementing write() method write memory model required.


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