verilog - ERROR: HDL COMPILER 806 -


i have written verilog code scrolling hello world on 7 segment display of basys2 board. after compiling code getting error this-

"error:hdlcompiler:806 - "c:/users/vishakha.ramani/xilinx/scrollsevensegment/ssevenseg.v" line 214: syntax error near "endmodule"."

kindly tell me making mistake.

enter code here  module ssevenseg( input clock,  input reset,  output a, output b, output c, output d, output e, output f, output g, output [3:0] en );  reg [3:0] in0, in1, in2, in3;  // registers hold led value i.e data displayed reg [28:0] tick_tock;  // count every 1s i.e holds count of 50 m wire click;   @(posedge clock or posedge reset) begin if(reset) tick_tock <= 0; else if ( tick_tock==50000000) tick_tock <= 0; else tick_tock <= tick_tock+1; end  assign click = (( tick_tock==50000000)?1'b1:1'b0);  // click every second reg [3:0] count1;  // hold count upto 9 @(posedge click or posedge reset) begin  if (reset) count1 <= 0; else count1 <= count1 + 1; end    @ (*) begin case (count1) 8'b00000000 : begin in0 = 4'b0001;  // h in1 = 4'b0010;  // e in2 = 4'b0011;  // l in3 = 4'b0011;  // l end 8'b00000001 : begin in0 = 4'b0010;  // e in1 = 4'b0011;  // l in2 = 4'b0011;  // l in3 = 4'b0100;  // o end 8'b00000010 : begin in0 = 4'b0011;  // l in1 = 4'b0011;  // l in2 = 4'b0100;  // o in3 = 4'b0101;  // e end 8'b00000011 : begin in0 = 4'b0011; // l in1 = 4'b0100;  // o in2 = 4'b0101;  // e in3 = 4'b0100;  // o end 8'b00000100 : begin in0 = 4'b0100;  // o in1 = 4'b0101;  // e in2 = 4'b0100;  // o in3 = 4'b0110;  // r end 8'b00000101 : begin in0 = 4'b0101;  // e in1 = 4'b0100;  // o in2 = 4'b0110;   // r in3 = 4'b0011;  // l end 8'b00000110 : begin in0 = 4'b0100; in1 = 4'b0110; in2 = 4'b0011; in3 = 4'b0111; end endcase end   localparam n = 18;  reg [n-1:0]count;  // 18 bit counter allows multiplex @ 1000hz  @ (posedge clock or posedge reset ) begin if (reset) count <= 0; else count <= count +1; end  reg [3:0] display; reg [3:0] temp_en;  @ (*) begin case(count[n-1:n-2])     2'b00 :      begin     display = in0;     temp_en = 4'b0111;       end  2'b01:       begin       display = in1;      temp_en = 4'b1011;      end     2'b10:      begin     display = in2;     temp_en = 4'b1101;     end     2'b11:       begin     display = in3;     temp_en = 4'b1110;     end   endcase  end     assign en = temp_en;    reg [6:0] temp_display;    @(*) begin  case (display)  4'b0000 : temp_display = 7'b1111110;  // if give input '0' nothing except '-' displayed 4'b0001 : temp_display = 7'b1001000;  // display 'h' 4'b0010 : temp_display = 7'b0110000;  // display 'e' 4'b0011 : temp_display = 7'b1110001; // display 'l' 4'b0100 : temp_display = 7'b0000001; // display 'o' 4'b0101 : temp_display = 7'b1111010; // display 'r' 4'b0110 : temp_display = 7'b1000010; // display 'd'  default : temp_display = 7'b1111111; // blank  endcase end  assign {a,b,c,d,e,f,g} = temp_display       endmodule 

you appear missing semicolon after second-last statement:

assign {a,b,c,d,e,f,g} = temp_display 

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