system verilog - in UVM RAL, a reg defined as no reset value, but set/update a '0' data on it won't trigger bus transaction -

in ral file, have like:

class ral_reg_aaa_0 extends uvm_reg; rand uvm_reg_field r2y;  constraint r2y_default { }  function new(string name = "aaa_0");     super.new(name, 32,build_coverage(uvm_no_coverage)); endfunction: new virtual function void build();   this.r2y = uvm_reg_field::type_id::create("r2y",,get_full_name());   this.r2y.configure(this, 12, 4, "rw", 0, 12'h0, 0, 1, 1); endfunction: build  `uvm_object_utils(ral_reg_aaa_0)  endclass : ral_reg_aaa_0 

you can find r2y set has_reset = 0, in real rtl, it's 'x' value default if use set/update mechanism write reg, if write data 0, equal reset value in r2y (even has_reset = 0), seems ral treat m_mirror == m_desired there won't bus transaction reg access.

like env.regmodel.aaa_0.r2y.set(0); env.regmodel.aaa_0.update(status,uvm_frontdoor); 

does make sense? thought no matter value set these kind of regs, there should bus transaction happening.

ps: mirrored , desired values 2-state vectors, , reg fields set 'no reset' value, m_mirrored initial value reg field still 0. if rtl reset value "x", instance, there 10 regs in design, want randomly pick number of them write them random value (of course, 0 legal value), seems miss '0' value register setting in case. using workaround now, flush regs 0 value 'write' ral method, can meet expectation overhead on bus

the internal representations of mirrored , desired values 2-state vectors , stored on per field basis. means when created, r2y field's mirrored value 0. setting desired value 0, values still same, why no bus transaction started. if want force bus transaction, use write(...) method:

env.regmodel.aaa_0.write(status, 0);  // write value '0' register 

if still want use set(...) play register fields, try like:

env.regmodel.aaa_0.r2y.set(0); env.regmodel.aaa_0.write(status, env.regmodel.aaa_0.get());